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CXG1104TN
High Power SPDT Switch with Logic Control
Description The CXG1104TN is a high power antenna switch MMIC for use in cellular handsets, for example, CDMA. The CXG1104TN has on-chip logic, which enables the switch circuit to operate by 1 CMOS control line. The Sony JFET process is used for low insertion loss and on-chip logic circuit. Features * Low insertion loss: 0.3dB @900MHz, 0.4dB @1.9GHz * High linearity: IIP3 (Typ.) = 70dBm * 1 CMOS compatible control line * Small package size: 10-pin TSSOP Applications Cellular handsets, for example, narrow band CDMA and wide band CDMA Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25C) * Bias voltage VDD * Control voltage * Operating temperature * Storage temperature Vctl Topr Tstg 10 pin TSSOP (Plastic)
7 5 -35 to +85 -65 to +150
V V C C
GaAs MMICs are ESD sensitive devices. Special handling precautions are required. The actual ESD test data will be available later.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E00X23A2Z-PS
CXG1104TN
Block Diagram and Recommended Circuit
Rctl (1k) CTL Cbypass (100pF) GND 6 5 Cbypass (100pF) CRF (100pF) GND 8 3 GND VDD
7
4
RF1
GND RF2 CRF (100pF)
9
2
GND
10
1 CRF (100pF)
RF3
When using this IC, the following external components should be used: Rctl: This resistor is used to improve ESD performance. 1k is recommended. CRF: This capacitor is used for RF decoupling and must be used for all applications. 100pF is recommended. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended.
Truth Table On Pass RF1 - RF2 RF1 - RF3 CTL L H
DC Bias Condition Item Vctl (H) Vctl (L) VDD Min. 2.0 0 2.6 Typ. 3.0 -- 3.0 Max. 3.6 0.8 4.5
(Ta = 25C) Unit V V V
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CXG1104TN
Electrical Characteristics Item Insertion loss Isolation VSWR Harmonics 1dB compression input power Input IP3 Switching speed Control current Bias current Symbol IL ISO. VSWR 2fo 3fo P1dB IIP3 TSW Ictl IDD Vctl (High) = 3V VDD = 3V 900MHz 1.9GHz 900MHz 1.9GHz 900MHz, 1.9GHz 1 1 VDD = 3.0V, 0/3V control 2 20 14 -60 -60 32 60 Condition
(Ta = 25C) Min. Typ. Max. Unit 0.30 0.55 0.40 0.65 23 16.5 1.2 -75 -75 35 70 2 40 100 5 80 200 1.4 dB dB dB dB -- dBc dBc dBm dBm s A A
1 Pin = 29dBm, 900MHz, VDD = 3.0V, 0/3V control 2 Pin = 25dBm (900MHz) + 25dBm (901MHz), VDD = 3.0V, 0/3V control
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CXG1104TN
Package Outline
Unit: mm
2.8 0.1 10
10PIN TSSOP (PLASTIC)
1.2MAX 0.1 6
2.2 0.1
+ 0.15 0.1 - 0.05
3.2 0.2
1
5 0.5 0.25 0 to 10
+ 0.08 0.22 - 0.07
0.1
M
(0.2) + 0.08 0.22 - 0.07
DETAIL A
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-10P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02g
10PIN TSSOP (PLASTIC)
1.2MAX 2.8 0.1 10 6 0.1
(0.1) + 0.025 0.12 - 0.015
+ 0.15 0.1 - 0.05 0.25 0 to 10 DETAIL A
EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02g
A
2.2 0.1
3.2 0.2
1
5 0.5
+ 0.08 0.22 - 0.07
0.1
M
(0.2) + 0.08 0.22 - 0.07
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-10P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m
(0.1) + 0.025 0.12 - 0.015
A
0.45 0.15
0.45 0.15
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Sony Corporation

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